Serial communications is a process that involves sequentially communicating a stream of data bits over a serial communications link. Serial communications is used in a wide variety of applications, many of which are defined by their own unique standards. A few examples include, the Serial Advanced Technology Attachment (SATA) standard, which sets forth serial communication specifications for transferring data between a computing device (e.g., a personal computer) and a data storage device (e.g., a computer hard drive); the Universal Serial Bus (UBS) standard, which specifies the transfer of data between a computing device and a peripheral device; and the DigRF standard, which specifies a digital serial communications link between a baseband controller and radio in a cellular handset.
FIG. 1 is a drawing of a typical two-way serial communications system 100 having differential upstream and downstream serial links 102 and 104. The two-way serial communications system 100 includes an uplink line driver (LD) 106, an uplink line receiver (LR) 108, a downlink LD 110, and a downlink LR 112. The uplink LD 106 is configured to transmit a digital data stream comprised of a sequence of data bits upstream to the uplink LR 108, via the upstream serial link 102. Similarly, the downlink LD 110 is configured to transmit a digital data stream downstream to the downlink LR 112, via the downstream serial link 104.
The uplink LD 106 is clocked by a first high-frequency clock, and the downlink LD 110 is clocked by an independently generated second high-frequency clock. The first high-frequency clock is generated by a first clock synthesizer 114, based on a first low-frequency clock provided by a first oscillator 116. The second high-frequency clock is generated by a second clock synthesizer 118, based on a second low-frequency clock provided by a second oscillator 120.
Because the first and second high frequency clocks are not transmitted along with the data streams, and the LRs 108 and 112 are not otherwise synchronized with the LD clocks, some phase alignment mechanism must be provided to establish proper phase relationships between the local clocks at the LRs 108 and 112 and the data bits received by the LRs 108 and 112. First and second clock recovery circuits 122 and 124, which are coupled to the uplink and downlink LRs 108 and 112, respectively, serve to perform these phase alignment processes.
It is not uncommon for the phase or frequency of data streams received by one of the LRs 108 and 112 to change or fluctuate over time. To track these changes and fluctuations, each of the clock recovery circuits 122 and 124 is typically implemented within a phase-locked loop (PLL). FIG. 2 is a drawing of a typical PLL-based (or “tracking”) clock and data recovery (CDR) circuit 200. The PLL-based CDR circuit 200 comprises a sampling phase detector 202, a charge pump 204, a loop filter 206, and a multi-phase voltage controlled oscillator (VCO) 208. The multi-phase VCO 208 operates to generate a multi-phase set of sampling clocks, for example, clk1, clk2, clk3. The sampling phase detector 202 is configured to receive the multi-phase set of sampling clocks, clk1, clk2, clk3, and use the clocks to sample the incoming data stream. Based on the phase and frequency relationship of the multi-phase set of sampling clocks, clk1, clk2, clk3 and the sampled data, the sampling phase detector 202 generates phase error pulses, Pu and Pd. As explained in more detail below, the charge pump 204 and loop filter 206 respond to these phase error pulses, Pu and Pd, by increasing or decreasing the value of a control voltage signal, ΔVin, applied to the multi-phase VCO 208. The multi-phase VCO 208 responds to changes in the control voltage signal, ΔVin, by increasing or decreasing the frequency of the multi-phase set of sampling clocks. The frequency-corrected multi-phase set of sampling clocks is then fed back to the sampling phase detector 202, which then samples the incoming data stream using the frequency corrected multi-phase set of sampling clocks. The above described process is repeated again and again until the phase error between the multi-phase set of sampling clocks and the clock being recovered from the incoming data is reduced to zero (or some acceptably small amount).
The sampling phase detector 202 in the PLL-based CDR circuit 200 is often comprised of what is known as a “bang-bang” phase detector, a circuit diagram of which is shown in FIG. 3A. The bang-bang phase detector 300 includes first, second and third flip-flops 302-1, 302-2 and 302-3, which are configured to sample the incoming data stream according to the multi-phase set of sampling clocks, clk1, clk2, clk3. Each of the sampling clocks in the multi-phase set of sampling clocks, clk1, clk2, clk3, has the same nominal frequency. However, each individual sampling clock in the set is offset in phase relative to other sampling clocks in the set. More specifically, and as illustrated in the timing diagrams in FIG. 3B, the second sampling clock, clk2, is delayed relative to the first sampling clock, clk1, by ninety degrees, and the third sampling clock, clk3, is delayed relative to the first sampling clock, clk1, by one hundred eighty degrees.
The input data stream is sampled by the first, second and third flip-flops 302-1, 302-2 and 302-3 upon the occurrences of rising edges of the three sampling clocks, clk1, clk2 and clk3. The resulting data samples are coupled to first and second exclusive-OR (XOR) gates 304-1 and 304-2. In addition to serving as a sampling clock for the third flip-flop 302-3, the third sampling clock, clk3, is used to control the enable of the first and second XOR gates 304-1 and 304-2, and to synchronize the phase error pulses, Pu and Pd. A delay element 306 having a delay of equal to one flip-flop delay is inserted in the path of third sampling clock, clk3, so that the enable signals and phase error pulses, Pu and Pd, are properly timed.
The multi-phase set of sampling clocks, clk1, clk2, clk3, is configured in this case so that data transitions in the input data stream occur either between the rising edges of the first and second sampling clocks, clk1 and clk2, or between the rising edges of the second and third sampling clocks, clk2 and clk3. If a data transition occurs between the rising edges of the first and second sampling clocks, clk1 and clk2, the frequency of the clock being recovered is deemed to be lagging the data (frequency too low), and a phase error pulse, Pu, is generated at the output of the first XOR gate 304-1. On the other hand, if a data transition occurs between the second and third sampling clocks, clk2 and clk3, the frequency of the clock being recovered is deemed to be leading the data (frequency too high) and a phase error pulse, Pd, is generated at the output of the second XOR gate 304-2.
The Pu and Pd phase error pulses generated by the first and second XOR gates 304-1 and 304-2 are used to control the charge pump 204 and loop filter 206. As illustrated in FIG. 3C, a positive current source responds to Pu phase error pulses by sourcing current to the loop filter 206, and a negative current source responds to Pd phase error pulses by sinking current from the loop filter 206. Because the loop filter 206 operates as an integrator, the VCO control voltage, ΔVin, increases or decreases depending on whether the charge pump 204 receives a Pu phase error pulse or a Pd phase error pulse respectively. More particularly, receipt of a Pu phase error pulse will result in an acceleration of the VCO output phase, while receipt of a Pd phase error pulse will result in a deceleration of the VCO output phase.
While the PLL-based CDR circuit 300 is capable of regenerating a recovered clock at the LR of a serial communications link, actual data cannot be sent to the LR until the frequency correction process (i.e., “acquisition” process) described above has completed. In other words, before actual data is sent over the link, the PLL must operate to lock to a training sequence (or “header”) having a predefined transition pattern that facilitates the acquisition process. Only until after the acquisition process is completed can actual data be reliably communicated over the communications link to the LR.
Because the PLL-based CDR circuit acquisition process is an averaging process implemented in a feedback and control system, it takes on the order of a thousand training sequence bits (i.e., a thousand “unit intervals” (UIs) or more) to complete the acquisition process. This large “header overhead” is highly undesirable since it not only delays actual data communications, but also results in wasted power. To avoid having to unnecessarily repeat the time consuming acquisition process, PLL-based CDR circuits are also typically configured to run continuously, even when the communication link is idle. Unfortunately, running the PLL at all times wastes additional power.
Another problem with the PLL-based CDR circuit 300 is that it is fundamentally incapable of operating in the presence of large frequency errors that can exist between the frequency of the clock being recovered and the multi-phase set of sampling clocks, clk1, clk2, clk3. This is attributable to limits on the possible loop bandwidth of the PLL. The actual frequency of the clock being recovered must therefore be very close in frequency to the frequency of the multi-phase set of sampling clocks, clk1, clk2, clk3, or the PLL will be unable to acquire or lock to the data in the received data stream.
Finally, in order for the PLL-based CDR circuit 300 to work properly, the data streams received by the LRs 108 and 112 must exhibit jitter-open eye patterns. In other words, the peak-to-peak jitter in the data stream received by the LRs 108 and 112 must remain less than a single UI. Otherwise, the PLL-based CDR circuit 300 will be either incapable of recovering the clock and data or the recovered data will have an unacceptably high error rate.
Given the foregoing problems and limitations of the prior art, it would be desirable to have systems and methods for recovering clocks and data in serial communications systems that: are not burdened by large header overheads and time consuming acquisition processes; do not require a PLL or feedback to recover the clocks and data; continue to operate properly even when large frequency errors and high jitter are present; and do not consume large amounts of unnecessary power.